Rapid Prototyping of Embedded Video Processing Systems in FPGA Devices

Design of video processing circuits requires a variety of tools and knowledge, and it is difficult to find the right combination of tools for an efficient design process, specifically when considering open tools for evaluation or educational purpose. This chapter presents an overview of video processing requirements, programmable devices used for embedded video processing and the components of a video processing chain. We propose a novel design flow for generating customizable intellectual property (IP) cores used in streaming video processing applications. This design flow is based on domain-specific modules in Python language. Examples of generated cores are presented

Adherence to physical activity recommendations and the influence of socio-demographic correlates – a population-based cross-sectional study

<p>Abstract</p> <p>Background</p> <p>Current physical activity guidelines acknowledge the importance of total health enhancing physical activity (HEPA) compared to leisure time physical activity or exercise alone. Assessing total HEPA may result in different levels of adherence to these as well as the strength and/or direction of associations observed between total HEPA and socio-demographic correlates. The aim of this study was to estimate the proportion of the population adhering to the recommendation of at least 30 minutes of HEPA on most days, and to examine the influences of socio-demographic correlates on reaching this recommendation.</p> <p>Methods</p> <p>Swedish adults aged 18–74 years (n = 1470) were categorized, based on population data obtained using the IPAQ, into low, moderately and highly physically active categories. Independent associations between the physical activity categories and socio-demographic correlates were studied using a multinomial logistic regression.</p> <p>Results</p> <p>Of the subjects, 63% (95% CI: 60.5–65.4) adhered to the HEPA recommendation. Most likely to reach the highly physical active category were those aged < 35 years (OR = 1.8; 95% CI: 1.1–3.3), living in small towns (OR = 1.8; 95% CI: 1.1–2.7) and villages (OR = 2.4; 95% CI: 1.6–3.7), having a BMI between 25.0–29.9 kg/m²(OR = 2.7; 95% CI: 1.4–5.3) having a BMI < 25 kg/m²(OR = 2.5; 95% CI: 1.3–4.9), or having very good (OR = 2.1; 95% CI: 1.3–3.3) or excellent self-perceived health (OR = 4.1; 95% CI: 2.4–6.8). Less likely to reach the high category were women (OR = 0.6; 95% CI: 0.5–0.9) and those with a university degree (OR = 0.5; 95% CI: 0.3–0.9). Similar, but less pronounced associations were observed for the moderate group. Gender-specific patterns were also observed.</p> <p>Conclusion</p> <p>Almost two-thirds of the Swedish adult population adhered to the physical activity recommendation. Due to a large diversity in levels of physical activity among population subgroups, social-ecological approaches to physical activity promotion may be warranted.</p

SHDL—A Hardware Description Language and Open-Source Web Tool for Online Digital Systems Design Teaching

Hardware description languages and tools require a considerable amount of teaching activities in a digital systems design course, which is difficult to accommodate in a limited time frame, and to use for e-learning. This paper presents our user-friendly and open-source web-based digital design tool, SHDL, which is used to describe and simulate hardware components and translate them into a standard language. SHDL is a teaching language and tool for digital design, which aims to improve the teaching and learning experience in digital systems design courses. The use and evaluation of the proposed online teaching model for the Digital Electronic Systems Design (DESD) course, using the SHDL tool for e-learning during the COVID-19 phase, is presented. Using the SHDL language and web tool, we have created many examples of digital circuits that prepare students to explore their own designs. The example components can also be used as digital system modules, leading to better modularity of the final project. The use of SHDL in the DESD course has shown that the proposed language leads to fewer syntax, simulation and synthesis errors in the designed circuits. The evaluation results show that at the end of the laboratory exercises, there was no longer a difference in knowledge between the students without prior VHDL experience and the other students. The results encourage us to continue using SHDL, and to complement the traditional DESD teaching methods with e-learning

A modelling-based methodology for evaluating the performance of a real-time embedded control system

International audienc

From high-level real-time software design to low level hardware simulation : a methodology to evaluate performances of control embedded systems

International audienc

PET-to-MLIR: A polyhedral front-end for MLIR

We present PET-to-MLIR, a new tool to enter the MLIR compiler framework from C source. The tool is based on the popular PET and ISL libraries for extracting and manipulating quasi-affine sets and relations, and Loop Tactics, a declarative optimizer. The use of PET brings advanced diagnosis and full support for C by relying on the Clang parser. ISL allows easy manipulation of the polyhedral representation and efficient code generation. Loop Tactics, on the other hand, enable us to detect computational motifs transparently and lift the entry point in MLIR, thus enabling domain-specific optimizations in general-purpose code. We demonstrate our tool using the Polybench/C benchmark suite and show that it can lower most of the benchmarks to the MLIR’s affine dialect successfully. We believe that our tool can benefit research in the compiler community by providing an automatic way to translate C code to the MLIR affine dialect

μ-Genie: A Framework for Memory-Aware Spatial Processor Architecture Co-Design Exploration

Spatial processor architectures are essential to meet the increasing demand in performance and energy efficiency of both embedded and high performance computing systems. Due to the growing performance gap between memories and processors, the memory system of ten determines the overall performance and power consumption in silicon. The interdependency between memory system and spatial processor architectures suggests that they should be co-designed. For the same reason, state-of-The-Art design methodologies for processor architectures are ineffective for spatial processor architectures because they do not include the memory system. In this paper, we present μ-Genie: An automated framework for co-design-space exploration of spatial processor architecture and the memory system, starting from an application description in a high-level programming language. In addition, we propose a spatial processor architecture template that can be configured at design-Time for optimal hardware implementation. To demonstrate the effectiveness of our approach, we show a case study of co-designing a spatial processor using different memory technologies

Design and management of image processing pipelines within CPS: 2 years of experience from the FitOptiVis ECSEL Project

Cyber-Physical Systems (CPS) are dynamic and reactive systems interacting with processes, environment and, sometimes, humans. They are often distributed with sensors and actuators, smart, adaptive, predictive and react in real-Time. Indeed, as sight for human beings, image-and video-processing pipelines are a prime source for environmental information for systems allowing them to take better decisions according to what they see. Therefore, in FitOptiVis we are developing novel methods and tools to integrate complex image and video processing pipelines. FitOptiVis aims to deliver a reference architecture for describing and optimizing quality and resource management for imaging and video pipelines in CPS both at design-and run-Time. The architecture is concretized in low-power, high-performance, smart components, and in methods and tools for combined design-Time and run-Time multi-objective optimization and adaptation within system and environment constraints